Job Description Work in Analog/Mixed-Signal Design Verification Methodology Development group to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows, and work hands-on with AMS IP Teams for AMS DV flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with digital design, analog design, analog behavioral modeling and design verification teams, apply and advance existing and evolving Digital and AMS Verification methodologies and processes, and contribute to establish and maintain Verification Platform to ensure High Quality and High Efficiency of Pre-Si Verification Delivery towards high quality silicon products.
•Work in methodology development team to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows.
• Work with teams to enable deployment of new flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as SERDES, etc) and integration.
• Document on new flows and processes for AMS DV.
• Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures.
• Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements.
• Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support.
Job Locations:
• Taiwan: Hsinchu/Taipei
• India: Bangalore
• Singapore
• USA: Santa Clara, CA/San Diego, CA

#LI-LL1 Requirement• Quick learner with strong critical thinking and creative problem-solving skills.
• Solid knowledge in ASIC design process, computer architecture, digital design and UVM-based design verification methodologies.
• Proficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA).
• Proficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc.
• Proficient on Design Verification development process, from specification to test plan, to configurable test bench, drivers and checkers setup, to test suite building to meet functional and code coverage goals, and power-aware simulations and gate level simulations.
• 5+ years ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal cores and/or chips.
• Familiar with programming languages: C, C++, and/or System C.
• Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., CVS, Perforce, etc.) is a plus.
• Knowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus
• Design or Verification work experience on Wireless and/or Wired Interface Standards, such as Wi Fi and SERDES, etc., is a plus.