Job Description•Work in methodology development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows.•Work with teams to enable deployment of new AMS Behavioral Modeling flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as RF, etc) and integration.

•Document on new flows and processes for AMS Behavioral Modeling.•Apply wide range of AMS Behavioral Modeling skills to help and support AMS IP or Chip Teams to establish or enhance new or existing Modeling capabilities, including but not limited to Model Development, Model Validation to ensure Consistency of Behavior with Original Circuit, Integration of Models into various Verification Environment, fixing Modeling issues found in simulation, etc.

•Contribute to continuous improving on AMS Behavioral Modeling process for better quality and efficiency through methodology and process improvements.

•Communicate and collaborate with global architecture, design, verification teams to address new needs or requirement on AMS Behavioral Modeling.

Job Locations:•Taiwan: Hsinchu/Taipei•India: Bangalore•China: Beijing/Hefei•Singapore•USA: Santa Clara, CA/San Diego, CARequirement•Strong critical thinking and creative problem-solving skills.•Proficient on Verilog and System Verilog, able to develop synthesizable and behavioral code•Deep knowledge on digital design fundamentals, including Finite State Machine, etc.•Able to read schematics of Analog or Custom Design•Able to run and debug HDL and SPICE simulations•Good Understanding of simple Analog Mixed-Signal design elements such as op-amps, etc.•Hands on experiences with EDA tools such as Cadence Virtuoso DE •Previous experience on analog behavioral modeling is a huge advantage.•Ability to develop System Verilog Assertion is a strong plus•Experience on Digital and/or AMS Functional Verification is a strong plus•Knowledge of systems such as SERDES, PLL and/or Wi Fi, etc., is a strong plus•Ability to develop Verilog-A or Verilog-AMS models is a strong plus•Ability to develop Model Validation Environment is a strong plus•Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., CVS, Perforce, etc.) is a plus.