這份工作已經過期了。

廣告



Design Verification Engineer_hsinchu, Hsinchu

發表 2024-02-11
過期 2024-02-17
ID #2026538229
Free
Design Verification Engineer_hsinchu, Hsinchu
Taiwan, 新竹縣, 新竹,
發表 February 11, 2024

描述

Job Description As deep sub-micron process requires longer research cycle and higher manufacture cost, DV(design verification) has become an inevitable part of design group in Mediatek chip development flow. CDG DV is in charge of development and implementation of smart phone, TV, and ASIC product line verification plan.

 It included: integrated simulation/verification env development, big data analysis and efficiency improvement, bus fabric / EMI (External memory interface ) / Low power functions verification plan and implementation  Need to build up verification plan/bench and continuously improve methodology, and you will understand both detail scenario and global view of cell phone/ASIC operating schemes Need to leverage the latest EDA tool and concept to accomplish the verification plan Requirement1.

Have a good command of Verilog / System Verilog / C++ / Perl2.

Have good senses of UVM and Formal verification method.3.

ARM Based SOC verification experience is a plus.4.

Chip Level verification experience is a plus.

5.

Well Organized, methodical, and detail oriented.6.

Must be a team player and easy to work with

職位詳情

工作類型: 全職
合同類型: 永恆的
薪酬類型: 每月
職業: Design verification engineer_hsinchu

⇐ 之前的工作

下一份工作 ⇒     

 

聯繫雇主

    雇主信息

    Mediatek

    快速搜索:

    地點

    輸入城市或地區

    關鍵詞


    廣告