Responsible for technical management of external DRAM suppliers, foundry partners and Product Management , ensuring alignment on technology readiness, yield, quality, reliability, and long‑term roadmap execution . Operates as a senior technical authority and key interface between Product Engineering, Designers and other internal engineering teams and memory partners, influencing outcomes across multiple programs.
Primary focus is on DRAM but HBM experience is desirable, but not essential
Key Responsibilities Responsible for day‑to‑day technical engagement and management of DRAM suppliers and partners Lead supplier technical reviews covering roadmap alignment, yield, quality, and risk Drive joint yield improvement and issue resolution across process, design, and test domains Interface with DRAM suppliers on process changes, defect reduction, and manufacturing readiness Support qualification and yield ramp from early silicon through high‑volume manufacturing Analyze inline, WAT, and test data to identify yield, variability, and reliability issues Collobrate with internal product requirements into clear, actionable supplier technical direction Provide technical assessments, recommendations, and escalations to senior engineering leadership Support the second‑source strategy and supply continuity planning
Qualifications
MS or Ph D in Electrical Engineering, Materials Science, Physics, or related field
10+ years of experience in DRAM technology, process integration, yield engineering, or supplier‑facing roles Demonstrated experience working directly with external DRAM suppliers Strong understanding of DRAM process, yield mechanisms, and reliability physics
Additional Information
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