We are looking for a signal and power integrity (SI/PI) Engineer – someone who is excited to join a growing group of diverse individuals responsible for chip package and PCB design analysis to achieve high-speed mixed-signal circuit design challenge, such as DP2.1, PCI-Express Gen6, and even 100 Gb E or beyond.

NVIDIA has continuously reinvented itself over two decades.

Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing.

More recently, GPU deep learning ignited modern AI — the next era of computing.

NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world.

This is our life’s work, to amplify human creativity and intelligence.

What you'll be doing: Work on crafting creative Signal and Power Integrity solutions to complex system design problems System-level power integrity simulations of NVlinks 200 Gbs+, PCIe, and other HSIO such as DP2.1/HDMI2.1/CSI/USB4.

Design and optimize Power Delivery Network (PDN) across interposers, packages, and PCBs.

SI channel analysis for spec development: DP2.1/HDMI FRL2.

Constant improvements of SI/PI models through lab measurements Simulation automation, data gathering, analysis and visualization using JMP, MATLAB or similar tools.

Opportunity to work in dynamic cross-functional role to optimize package, PCB, ASIC, mixed signal circuit.

Post-layout SI/PI model extraction for project review sign-off.

What we need to see: BS/MS-Electrical Engineering or equivalent experience.

3+ years of industry experience.

Strong understanding of electromagnetics including transmission line theory and via properties, and the SI/PI/EMI applications; S/Y/Z parameters; discrete signal processing knowledge.

Hands on use of 3/2.5-D modeling tools like ANSYS HFSS/Q3 D/SIwave, Cadence Power SI.

Experience with PDN evaluation using layout extraction tools for packages and PCBs and spice-based time domain simulations for power noise.

Experience with die power delivery modeling – mixed-signal blocks & digital and associated tools like CSM/Redhawk, Raptor-X.

Familiarity with voltage regulator modeling for board power supplies using simplis or spice.

Familiarity with use of VNA, TDR, DSO.

Familiarity with transient simulation in tools and understanding of eye diagram methodology.

Have measurement and simulation correlation experience.

Passionate about SI/PI work.

Ways to stand out from the crowd: Experience w/ Matlab, Python, VBS, or C for simulation automation.

Exposure to interface timing budgets and system modeling.

SI analysis flow including frequency and time domain simulation.

PDN analysis flow including model generation and time domain simulation.

PSIJ Analyses involving co-simulation of circuits and PDN models.

Familiarity with high-speed I/O design concepts including clock generation, transmitter & receiver design, and equalization schemes.

Develop novel algorithms & new methodologies to improve SI/PI/EMI modeling efforts.

Understanding of high-volume manufacturing variations and impact to channel signal integrity is a plus.