Job Description1.

Create the relative behavior model (Verilog format) based on the model spec of the analog part of power management integrated chip (PMIC)2.

According to the system requirements of the analog part of PMIC, identify the verification scenarios also execute your verilfication plan.3.

To write test bench, monitors and checkers by using constrained-random verification, System Verilog UVM, SVA, power aware simulation or formal equivalence checking Requirement Familiar with Verilog language Familiar with Synopsys VCSFamiliar with Synopsys Verdi Familiar with Perl/TCL/Python is a plus Familiar with System Verilog is a plus Familiar with UVM is a plus Familiar with Cadence/Synopsys AMS platform is a plus.

Familiar with Analog design flow is a plus.

Familiar with power management IC(PMIC) design is a plus.