WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE PERSON: The candidate is an experienced Package Layout or Silicon Physical Layout Engineer that has excellent communication & project management skills and can complete the design task with the least supervision. He/she must be able to work on a fast phase environment and collaborate well with others. KEY RESPONSIBILITIES: Codesign with Signal/Power Integrity and PCB design team to complete a substrate layout that will meet the design objectives for performance, cost and quality. Support substrate design for probe card substrate, test chips and test vehicles for technology development. Codesign with SOC team to complete Bump matrix and Interposer design for 3 D,2.5 D, COWOS and other advanced packaging technologies (Chiplet). Contribute to the development and enhancements of processes and methodologies to improve design efficiency. Interact with Assembly houses and substrate vendors to achieve cost-efficient and high-quality design. Mentor Junior Colleagues to enhance layout practices. PREFERRED EXPERIENCE: Minimum 5 years’ experience in designing complex substrate design or Silicon Interposers. Very good understanding of Signal Integrity and power integrity principles. Knowledge of using CAD Layout tools such as Cadence SIP, APD, Synopsys 3 DICC, First Encounter, ICC2 or other Packaging or Silicon Physical Layout Software. Knowledge of Python, TCL, Perl or Skill Script Programming is a plus. Experience dealing with assembly, foundry, and substrate vendors. ACADEMIC CREDENTIALS: B. A. Sc. in Electrical Engineering, Computer Engineering, or Engineering Science LOCATION: Hsinchu, Taiwan #LI-SC1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. THE PERSON: The candidate is an experienced Package Layout or Silicon Physical Layout Engineer that has excellent communication & project management skills and can complete the design task with the least supervision. He/she must be able to work on a fast phase environment and collaborate well with others. KEY RESPONSIBILITIES: Codesign with Signal/Power Integrity and PCB design team to complete a substrate layout that will meet the design objectives for performance, cost and quality. Support substrate design for probe card substrate, test chips and test vehicles for technology development. Codesign with SOC team to complete Bump matrix and Interposer design for 3 D,2.5 D, COWOS and other advanced packaging technologies (Chiplet). Contribute to the development and enhancements of processes and methodologies to improve design efficiency. Interact with Assembly houses and substrate vendors to achieve cost-efficient and high-quality design. Mentor Junior Colleagues to enhance layout practices. PREFERRED EXPERIENCE: Minimum 5 years’ experience in designing complex substrate design or Silicon Interposers. Very good understanding of Signal Integrity and power integrity principles. Knowledge of using CAD Layout tools such as Cadence SIP, APD, Synopsys 3 DICC, First Encounter, ICC2 or other Packaging or Silicon Physical Layout Software. Knowledge of Python, TCL, Perl or Skill Script Programming is a plus. Experience dealing with assembly, foundry, and substrate vendors. ACADEMIC CREDENTIALS: B. A. Sc. in Electrical Engineering, Computer Engineering, or Engineering Science LOCATION: Hsinchu, Taiwan #LI-SC1
