The successful candidate shall possess abundant experience in designing complex DSP for communication systems.

She/he shall also have decent knowledge in analog/mixed-signal circuitry to perform the modeling and optimization of the overall high-performance front ends for communication So Cs.

Essential Functions and Key Responsibilities:• Model the circuit blocks and mixed-signal IPs, including but not limited to high-speed ADCs, DACs, CTLE, FFE, and PLLs, to work with the architect and designers to achieve the optimal system-level performance.• Perform the functional verification and timing analysis on the IPs and the blocks.• Work with the digital verification team to generate the adequate interface to ensure the timing and connectivity.• Performs co-simulations on analog blocks and digital blocks in the mixed-signal simulation environment.

Mandatory Knowledge/Skills/Abilities:• Has intimate knowledge of UVM verification flow.• Have prominent tracking record in modeling and verification of analog/mixed-signal IPs, including but limited to SERDES, optical links, and wireless transmission systems.• Hands-on in modeling and simulating with System-Verilog (WREAL), Verilog-AMS, and/or C, C++.• Have a decent understanding in CMOS analog / mixed signal design.

Preferred Knowledge/Skill/Abilities:• Able to create IBIS-AMI model.• Can code in System-Verilog (WREAL).• Fluent in verbal and written communications.• Independently resolves issues and conquer design challenges.• Self-motivated and detail oriented.• Has good interpersonal skills.

Education and Experience Requirements:• M.

S.

in E. E.

with 8+ years’ experience, or Ph.

D.

in E. E.

with 6+ years’ experience (Supplement No.

1 to Part 740, Title 15)