這份工作已經過期了。

廣告



Vlsi Design Verification Engineer, Hsinchu

發表 2024-06-11
過期 2024-06-10
ID #2189085844
Free
Vlsi Design Verification Engineer, Hsinchu
Taiwan, 新竹縣, 新竹,
發表 June 11, 2024

描述

Job Description: At Ambarella, we gather brilliant minds together to push computer vision technology forward.

We're seeking a VLSI design verification (DV) engineer who will verify our most cutting-edge SOCs and components inside SOC.

A DV engineer works with designers to make sure design meets specification.

Firstly, a DV engineer creates a test plan.

A test plan plots in details on what tests you need/want to create and how you can apply the tests to the design under verification (DUV).

Secondly, a DV engineer writes a test bench which drives stimulus (a test) to DUV and writes monitor(s) and checker(s) to validate the DUV's outputs.

Thirdly, to fully verify a DUV, a DV engineer runs hundreds, thousands, or even millions of tests depending on the complexity of DUV - we call it regression.

A DV engineer then works with designer(s) to clean up all the failures in the regression.

Lastly and most importantly, a DV engineer must work with designers to review coverage data - it tells us whether all Verilog statements within DUV is truly and fully exercised or not so that we can guarantee the verification quality and deliver high quality designs Job Requirements:- + years of hands-on experiences on VLSI design verification- Experiences of transaction-based verification at higher-level of abstractions ( UVM) is a big plus.

職位詳情

工作類型: 全職
合同類型: 永恆的
薪酬類型: 每月
職業: Vlsi design verification engineer

⇐ 之前的工作

下一份工作 ⇒     

 

聯繫雇主

    快速搜索:

    地點

    輸入城市或地區

    關鍵詞


    廣告