Responsibilities Duties in this position will include: Testbench and test sequence development for verification of new controller technologies and features Functional coverage planning, coverage item coding, and test suite augmentation to achieve Functional Coverage Regression test development, monitoring, debug/triage, and correction to test environment, sequences, debug of controller RTL design.

Development & support of Verification environment scripting and capabilities Qualifications Bachelors Degree or above in EE/CS, minimum 10-15 years’ experience with HDL logic Design-Verification System Verilog / UVM testbench, Verilog/System Verilog logic design/RTL fluency a must Pre-existing Experience / familiarity with PCI-Express controller and protocol required.

Working experience with Python and TCL scripting languages preferred About Rambus With 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for today's most demanding applications.

From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable So C and system designers to deliver their vision of the future.